Question 4:
At the bottom of p. 13 and the top of p. 14 of the FOA, the following two sentences occur: "An institute and its members will need to be well integrated across the supply chain (Figure 2) to ensure wafers demonstrating the current state-of-the-art growth technologies are utilized in its device design, fabrication, and testing activities. However, materials growth or wafer processing improvements (i.e. defect density reduction, film thickness, yield, and diameter increases) are excluded from the scope of this FOA and the Institute's purpose." We would like to get some clarification on these two sentences, particularly the second, as it has been the source of some confusion.
First we should briefly describe our understanding of some term definitions. Normally, power devices are fabricated during a series of processing steps — including photolithography, gate dielectric deposition, etching, gate metallization, implantation, contact metallization, etc. -- that are each performed on the entire wafer. In common usage the term "wafer processing" refers to these steps. Individual devices can sometimes fail to undergo a processing step successfully; the percentage of devices which successfully undergo a given processing step is termed the "yield" for that step, and determine how robust and reliable the process is. (Metrology is used to help determine processing failure modes, and to increase yield. Increases in yield result in reductions in cost, which increase economic competitiveness.) When the processing of the wafer is complete, the individual power devices are diced out and then packaged.
A face-value interpretation of the second FOA sentence above would hold that the Institute should not work on improving wafer processing, or on increasing the yield of the processing steps involved in the fabrication of the power devices. In that case, only the dicing and packaging would be left as suitable topics for investigation. The development of new device architectures, requiring for example new gate dielectrics, different contact metals, different heteroepitaxy layers, etc. would thus be "excluded from the scope of this FOA." This would seem inconsistent with EERE's intent for the Institute, as described in other sections of the FOA.
A second, alternative interpretation, garnered from the context, is that the second sentence intends primarily to eliminate substrate research, but used the terms "wafer processing" and "yield" in an unconventional manner. This alternative interpretation is that growing boules of SiC, or performing synthesis of GaN substrates, are indeed beyond the scope of the institute. However, the growth of heteroepitaxial layers of active device material, the deposition of gate dielectric material, the exploration of alternative contact metal materials, etc. all remain legitimate topics for innovation. Similarly this interpretation would hold that the various wafer processing steps required to produce a functioning WBG power device — and the yield of those steps — are also legitimate topics for investigation and innovation within the scope of the Institute's activities.
Can you please comment on this discussion. And in particular, can you say which of the two interpretations are correct?
Answer 4:
The correct interpretation is the second because wafer processing is discussed within the context of materials growth, and specifically, defect density reduction, film thickness, yield, and diameter increases. Therefore, the interpretation that within this context substrate research is eliminated from the scope of this FOA, including as the questioner notes, SiC boule growth and GaN substrate synthesis, is correct. However, while the deposition of new gate dielectrics and alternative contact metals might be considered within the context of new and improved device designs and architectures, heteroepitaxial growth is not. Therefore, both substrate and epitaxial growth (including both heteroepitaxy and homoepitaxy) improvements are excluded from the scope of this FOA.
Question 22:
Question: Our question relates to funding for materials growth and wafer processing. We understand the use of funds to support solving materials growth and wafer processing improvements is not allow (as addressed in question 4 and 9 of the FAQ page) … however there are commercial and economic reasons why we would want to deploy funds and resources to ensure that the beginning of our supply chain (wafer processing and materials growth i.e. EPI) is healthy and is capable of supporting future production demands. Is the use of funding to support front-end suppliers for these purposes allowable?
Answer 22:
Response: As noted in Section I.B and the Merit Review Criterion Discussion in the Project Narrative guidance (Section IV.C.3), an Institute should enable and support "applied, research, development and demonstration projects." As such, the purpose of government funding for this Institute, as noted in the FOA goals, is to address device and module fabrication barriers and solve these challenges. As noted in Section I.C, an Institute will need to be well integrated across the supply chain with participation and contributions from both wafer and epitaxy manufacturers and suppliers in a form consistent with and articulated in a proposal's Approach and Management Plan (i.e. Operating Model) as referred to in Section IV.C.3, and consistent with the FOA goals, allocated resources, additional funding streams, and means of support.